1. Field of the Invention
The present invention relates in general to a write circuit of a Double Data Rate Synchronous DRAM (DDR SDRAM), and more particularly, to a write circuit of a DDR SDRAM, in which a clock domain crossing is generated from a writing driver during a data write operation and a proper data is always transferred to a gio bus line by using the delay of an internal data strobe signal's falling for a certain amount of time as an input data strobe bar signal, and at the same time, time is compensated when a skew is generated between a clock signal and a data strobe signal, thereby realizing a high-speed operation of a memory device.
2. Discussion of Related Art
Recently, a lot of attention has been paid to an interface with an external device to keep pace with a rapidly increasing operation speed of a DDR SDRAM. For example, in case of a data read operation, not only clock-related parameters tAC (DQ output access time from CK, /CK), tDQSCK (DQS output access time from CK, /CK) but all aspects of signal integrity including output slew rate, jitter, data eye, and duty also should be considered to realize a high speed operation for a mounting application. Fortunately though, the parameters like tAC and tDQSCK are provided with a DLL (Delay Locked Loop) circuit for adjusting a skew between a clock and data output in the DDR SDRAM, so it is relatively easy to adjust a parameter value.
On the other hand, in the case of a data write operation, both a data strobe's parameters tWPRE (write preamble), tWPST (write postamble) and parameters tDQSS (write command to first DQS rising edge) indicating a skew between a clock and a data strobe are important parameters. In the data write operation, however, the length of a clock and the length of a data strobe signal line on a PCB (Printed Circuit Board) for the mounting application are not often coincident, and input capacitance values thereof are also different. As a result of this, a skew is generated all the time.
Therefore, even though a tDQSS value for the mounting falls outside the permissible range from tDQSS_Min(=0.75tCK) to tDQSS_Max(=1.25tCK) or is within the permissible range, if a timing margin lacks due to any change in process, voltage, or temperature in a clock domain crossing area where an internal data strobe ids generated inside a chip an internal clock iclk meet, a malfunction occurs during the write operation.
To provide further details on the above problem, FIG. 1 presents a block diagram associated with a related art write operation, and its relevant timing diagrams are illustrated in FIG. 2, FIG. 3, and FIG. 4, respectively.
FIG. 1 is a block diagram of a write operation in a related art DDR SDRAM, and its structure and operations will be explained in the following.
A data input buffer 101 inputs an input data DIN and outputs an n-bit data, and the n-bit data is inputted to first and second n-bit data registers 108 and 109.
A data strobe generator 104 outputs a data strobe rising signal dsr and a data strobe falling signal dsf by using a data strobe DS inputted through a data strobe buffer 102. The data strobe rising signal dsr and the data strobe falling signal dsf are inputted to the first and second n-bit data registers 108 and 109, respectively. In case that a data is inputted on the rising edge of clock, the data strobe rising signal dsr is inputted to the first n-bit data register 108, while in case that a data is inputted on the falling edge of clock, the data strobe falling signal dsf is inputted to the second n-bit data register 109.
The first n-bit data register 108 inputs an n-bit data and a data strobe rising signal dsr, and the second bit data register 109 inputs an n-bit data and a data strobe falling signal dsf. Also, a third n-bit data register 110 inputs the data stored in the first n-bit data register 108 and the data strobe falling signal dsf. In this way, the data on the rising edge of the clock as well as the data on the falling edge of the clock are arranged on the falling edge of the data strobe. Here, the data inputted to the first and second n-bit data registers 108 and 109 should satisfy setup time and hold time of the internal data strobe, i.e., the data strobe rising signal dsr and the data strobe falling signal dsf, respectively.
Two kinds of n-bit data algn_rdata and algn_fdata arranged in the data strobe falling signal dsf are inputted to a multiplexer 113 through first and second delay units 111 and 112. The multiplexer 113 outputs an n-bit data mux_rdata, mux_fdata by using those signals. The output data mux_rdata, mux_fdata of the multiplexer 113 are inputted to a 2n-bit data register 114.
A clock generator 105 generates an internal clock iCLK by inputting a clock CLK and its inversion signal /CLK which are inputted through a clock input buffer 103. The internal clock iCLK generated by the clock generator 105 is inputted to an input data strobe generator 106 and a write strobe generator 107. The input data strobe generator 106 inputs the internal clock iCLK and a start address flag flag_SA and outputs a data input strobe even signal dinstb_e and a data input odd signal dinstb_o, and these signals are inputted to the 2n-bit data register 114. Here, the start address flag, flag_SA has a low or a high state value, depending whether a start address during a write operation is even or odd. For instance, if the start address is even, the data input strobe even signal dinstb_e is generated, while if the start address is odd, the data input strobe odd signal dinstb_o is generated. In addition, a write strobe generator 107 that has input the internal clock iCLK outputs a write strobe signal wtstb, and this signal is inputted to first and second write drivers 117 and 118.
The 2n-bit data register 114 changes, in response to the data input strobe even signal dinstb_e and the data input strobe odd signal dinstb_o outputted from the input data strobe generator 106, a clock domain of the data mux_rdata and mux_fdata outputted from the multiplexer 113, and classifies the data into an even data gio_edata and an odd data gio_odata. The even data gio_edata and the odd data gio_odata outputted from the 2n-bit data register 114 are inputted to the first and second write drivers 117 and 118 through first and second gio bus lines 115 and 116. However, if the timing between the output data mux_rdata and mux_fdata of the multiplexer 113 and the output signal dinstb_e and dinstb_o of the data strobe generator 106 is not right, a proper data cannot be transferred through first and second gio bus lines 115 and 116. After all, the timing is determined by a skew (or skews) between the internal data strobe falling signal dsf and the input data strobe signals dinstb_e and dinstb_o. These skews should be optimized in order to maximize a timing margin on both sides, by checking tDQSS_Min value as well as tDQSS_Max value of the data strobe signal DS and then adjusting delays of the first and second delays means 111 and 112 and the internal clock delay of the input data strobe generator 106. However, optimizing the skew against all changes in process, voltage and temperature is not always easy in real conditions. Especially in the case of a graphic memory with a high-speed operation, the tDQSS_Min and tDQSS_Max values are extremely small, so an even greater amount of efforts is required to control the skew more strictly.
Lastly, the first and second write drivers 117 and 118 store n-bit data gio_edata, gio_odata inputted through the first and second gio bus lines 115 and 116 in a DRAM core 119. More specifically, the write drivers are synchronized with a write strobe signal wtstb, which is generated by the write strobe generator 207 using the internal clock iCLK, and load the data on a local input/output (lio) bus line. In this case, the timing of the data write strobe signal wtstb is determined in consideration of the delays of the first and second gio bus lines 115 and 116 to the input data strobe signals dinstb_e and dinstb_o, and the set up time and the hold time of the first and second write drivers 117 and 118, respectively.
FIG. 2 and FIG. 3 are timing diagrams at tDQSS_Min and tDQSS_Max of the related art DDR SDRAM in FIG. 1.
FIG. 2 illustrates waveforms of each signal when a write command is inputted at T0, a burst length BL is 4, tDQSS is 0.75tCK, and a start address SA is even. At T1, the rising edge of the data strobe DS is inputted faster than the rising edge of the clock CLK by 0.25tCK. As a result, at T2, the input data strobe even signal dinstb_e, which is generated a short delay after the internal clock iCLK, has a shorter premargin pre_margin than the post margin post_margin for the output data of the multiplexer mux_rdata and mux_fdata.
On the other hand, FIG. 3 illustrates waveforms of each signal when a write command is inputted at T0, a burst length BL is 4, tDQSS is 1.25tCK, and a start address SA is odd. At T1, the rising edge of the data strobe DS is inputted later than the rising edge of the clock CLK by 0.25tCK. As a result, at T2, the input data strobe odd signal dinstb_o, which is generated a short delay after the internal clock iCLK, has a shorter premargin pre_margin than the post margin post_margin for the output data of the multiplexer mux_rdata and mux_fdata.
These two examples are illustrated in FIG. 4. FIG. 4 shows both cases where tDQSS and tDQSS values are faster or slower than the clock CLK. The timing diagram shows conditions for input data strobe signals dinstb_e and dinstb_o to obtain a maximum timing, and write pass and write fail conditions at the same time, in both cases of the multiplexer's output data mux_rdata/mux_fdata@tDQSS(fast) and mux_rdata/mux_fdata@tDQSS(slow).
As shown in FIG. 4, supposing that td=|tskew_dinstb−tskew_dsf−td_mux| and that the data delay time of the first and second delay units 111 and 112 explained in FIG. 1 is 0, for the input data strobe signals dinstb_e and dinstb_o to obtain a maximum timing margin from both perspectives of premargin, pre_margin, and post margin, post_margin, for the output data from the multiplexer, td should be equal to 0, i.e., td=0. That is to say, a relational expression tskew_dinstb=tskew_dsf+td_mux should be satisfied. In reality, however, it is almost impossible to satisfy the condition td=0 because of changes in process, voltage and temperature. Therefore, it is important to ensure that td is within a pass region. In such case, a condition of td<tvalid_data/2 should be satisfied, and since tvalid_data=tCK−(tDQSS_Max−tDQSS_Min)=0.5tCK within the permissible range of tDQSS_Min=0.75t CK and tDQSS_Max=1.25tCK, a condition of td<0.25tCK should be satisfied.
In the case of a graphic memory operating at tCK=3 ns (frequency=666 MHz), a maximum permissible skew td for all conditions including process, voltage and temperature should not exceed 0.75 ns. In fact, the maximum permissible skew td should be even smaller than 0.75 ds to leave a little margin. Also, as the operation frequency gets higher, the skew td of input data strobe signals dinstb_e and dinstb_o for the output data from the multiplexer should be controlled within an extremely small range, which, in reality, is a very difficult task to accomplish.